1. Field of the Invention
The present invention relates to a programmable input/output circuit for use in a programmable integrated circuit interfacing between an external circuit and an internal logic circuit, and to a programmable logic device incorporating such an input/output circuit. More specifically, the present invention relates to a programmable input/output circuit being capable of effective signal transfer between buses located interiorly and exteriorly of the programmable integrated circuit and being suitable for use in a programmable logic device with which a user can electrically program an arbitrary circuit of his own, and to a programmable logic device incorporating such a programmable input/output circuit.
2. Description of the Prior Art
A programmable logic device (herinafter, simply referred to as a PLD.) as well known in the art is an integrated circuit adapted to permit a user to establish therewith an arbitrary logic circuit of his own.
The PLD includes primarily a configurable programmable logic element (hereafter, simply referred to as a PLE.) for constructing a user's own logic, a memory cell for defining a circuit function, i.e. for determining the logical function of the PLE and a connection relation among internal wirings in the same, and a programmable input/output block (hereafter, simply referred to as an IOB.) for interfacing between external and internal logic circuits of the PLD.
The IOB 35 includes, as illustrated in FIG. 7 for example, an output terminal 12 connected to a programming wiring in the internal logic circuit, an input terminal 14 connected to a programmable wiring in the internal logic circuit, a pad 16 connected to the external circuit, an input buffer 18 for converting an external signal applied to the pad 16 to an internal logical level by detecting a threshold of the IOB 35 to assure compatibility between a TTL (1.4 V) level and a CMOS (2.5 V) level for example, a D flip-flop 20 of an edge trigger type for example for latching an output from the input buffer 18, a programmable two-input multiplexer 22 for transmitting one of outputs from the input buffer 18 and the D flip-flop 20 to the input terminal 14 in conformity with contents previously stored in a memory cell (not shown), an output buffer 24 for converting to a predetermined driving current an output signal of a high fan-out CMOS or TTL level led to the output terminal 12 and transmitting the converted driving current to the pad 16, and a three-input multiplexer 28 for controlling the output buffer 24 by switching it on and off or by two circuit-function-defining memory cells (not shown), each of which selects a tri-state buffer control in the internal logic circuit or by an IOB output control signal applied to an output control terminal 26.
Additionally, for provision of any bus in the PLD, there is known a technique disclosed for example in "Electronic Design", Jul. 11, 1985, P 111.
The prior PLDs however suffer from some difficulties as follows; there are independently disposed signal lines in which a bus connecting the respective PLEs in the PLD is connected on one side and a bus external to the PLD is connected, on the other side. In addition, an input terminal and an output terminal are separately provided. It is therefore difficult to directly introduce a signal on a bus located on a circuit board (a signal external to the integrated circuit) onto a bus located in the integrated circuit (PLD), and hence the introduction of the former signal is needed to be done utilizing another signal line. It is thus required until now, as illustrated in FIG. 8, upon connecting a bus 31 of an external integrated circuit 30 with a bus 36 of a logic circuit (LEe) 34 in the PLD 32, to first enter an external signal onto a programmable wiring 37 via an IOB 35 as illustrated in FIG. 7 for example and thereafter enter the same signal into the internal logic circuit 34 via the programmable wiring 37 including a switch 38 for switching the state of wiring. This requires many constituent circuit elements, particularly additional relaying elements, followed by time consuming operation, thus making impossible effective signal transfer.